As illustrated in FIG. 1, SRAMs (static random access memories) are characterized by having gate patterns 15 aligned, in a broken-line manner, perpendicularly to active regions 18. According to the example of FIG. 1, the SRAM has point-symmetric cell structures, and two transfer transistors and two CMOS (complementary metal oxide semiconductors) inverters are provided in each cell 100 symmetrically around a point.
In reducing the size of a SRAM, it becomes a key issue of how much a protruding amount B of each gate pattern 15 from the active region 18 can be reduced, as illustrated in the dashed-line box A. Next is described a current problem with a focus on, for example, driver transistors of the SRAM of FIG. 1.
FIG. 2 is an enlarged view of the region A of FIG. 1, and illustrates the setback position of a gate end portion created in a gate etching process. In general, end portions of gates 25 formed by the gate etching process are located in setback positions in resist patterns (gate patterns) 15. Therefore, the gate protruding amount B needs to be sufficiently provided in advance when the resist patterns are formed, in view of the setback amount of the gate etching. This, in turn, requires providing sufficient spacing “d″” between the active regions 18 in view of the setback amount of the gate etching, which prevents a reduction in the size of the SRAM device.
FIG. 3 illustrates a setback of the gate end portion after the gate etching and device failure. In the case where the gate protruding amount B (see FIG. 1) is sufficiently provided, the source and the drain are separated by the gate, as illustrated in FIG. 3A, and therefore, a favorable transistor may be formed. However, if the gate protruding amount is insufficient, the gate end is positioned posteriorly by exposure of polysilicon during the patterning process and the gate etching. As a result, as illustrated in FIGS. 3B and 3C, the gate end portion does not sufficiently overlap the active region (the source and drain). In particular, in the case of FIG. 3C, the source and the drain are not separated by the gate, causing a short circuit, and thus, the device is completely defective. In the case of FIG. 3B, although the source and the drain are separated by the gate and the sidewall, the gate length is different from that of the favorable device (FIG. 3A). Accordingly, there are differences in the device properties, and therefore, the device of FIG. 3B is also determined as defective.
The above description is given with an example of a driver transistor near a cell boundary; however, the same problem may occur for the protruding amounts of the transfer gates within the cells of FIG. 1.
Gate double patterning has recently attracted attention as a technology for preventing setbacks of gate etching end portions and decreasing cell sizes of SRAMs by reducing the space “d” between the active regions 18 of FIG. 2 (For example, see M. Kanda, et al, “Highly Stable 65 nm Node (CMOS5) 0.56 μm2 SRAM Cell Design for Very Low Operation Voltage”, 2003 Symposium on VLSI Technology Digest of Technical Papers, pp. 13-14). According to the technology, a single long gate pattern connecting adjacent gates is created first, and then etching is performed using a gate-separating mask 20 having an aperture 21 so as to form separated gates, as illustrated in FIGS. 4A through 4C. The technology does not cause setbacks of the gate end portions, and therefore, it is possible to reduce the space “d” between the active regions 18 of FIG. 2.
However, the inventors of the present disclosure have found a problem associated with the gate double patterning of FIGS. 4A through 4C. If the gate 25 is cut at a position very close to the active region (the source and drain region) due to displacement of the gate-separating mask 20 during the exposure process, as illustrated in FIG. 5A, and a device is then created according to general procedures, changes occur in the current characteristics of the gate end portion.
For example, four-way angled implantation is performed in order to form a pocket 26, as illustrated in FIG. 5B, then a sidewall (SW) 27 is formed by extension implantation, and a source-drain region 28 is formed, as illustrated in FIG. 5C. In this case, ion implantation characteristics are different between a region adjacent to the edge along the gate end portion and the remaining region. Therefore, variation is caused in the current characteristics (the arrow b) close to the edge of the gate and the current characteristics (the arrow a) of the inside the gate.
Devices produced in this manner cause property fluctuations, which become a factor of being defective. In order to prevent such property fluctuations, it is necessary to provide a sufficient amount of spacing “d” between the active regions 18 of FIG. 2 in view of a margin of exposure displacement of the gate-separating mask and an implantation margin even in the case of performing the gate double patterning.